1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device which includes an MOS transistor (insulated gate type field effect transistor) as a component. More particularly, the present invention relates to a structure for achieving the low power consumption and high speed operation of an MOS semiconductor integrated circuit device which can operate in a plurality of operation modes.
2. Description of the Background Art
FIG. 19 shows an example of the structure of a conventional semiconductor integrated circuit device disclosed in Japanese Patent Laying-Open No. 6-291267, for example.
In FIG. 19, the conventional semiconductor integrated circuit device includes CMOS inverters IVa, IVb, IVc and IVd of four stages cascaded between an input node 101 and an output node 102. Each of CMOS inverters IVa-IVd operates using a power supply voltage VDD applied on a power supply node and a ground voltage GND applied on a ground node as one and another operational power supply voltages. Each of the inverters inverts an applied signal for output.
CMOS inverters IVa-IVd include respective P channel MOS transistors Pa-Pd for outputting an H level signal and respective N channel MOS transistors Na-Nd for outputting an L level signal.
The semiconductor integrated circuit device further includes a first voltage generation circuit 110a commonly connected to the substrate regions (back gates) of P channel MOS transistors Pa-Pd and outputting a back gate voltage Vps in accordance with a control signal from a control circuit 112a, and a second voltage generation circuit 110b commonly connected to the substrate regions (back gates) of N channel MOS transistors Na-Nd and outputting a back gate voltage Vns in accordance with a control signal from a control circuit 112b. The operation will briefly be described below.
Now, consider the case in which output voltage Vps from first voltage generation circuit 110a is set to a voltage level which is slightly lower than power supply voltage VDD in accordance with the control signal from control circuit 112a, and output voltage Vns from second voltage generation circuit 110b is set to a voltage level which is slightly higher than ground voltage GND in accordance with the control signal from control circuit 112b.
In this case, when an input signal applied to input node 101 makes a transition from an L level to an H level, an output signal applied to output node 102 through CMOS inverters IVa-IVd of four stages makes a transition from the L level to the H level. When back gate voltage Vps of P channel MOS transistors Pa-Pd is lower than power supply voltage VDD, depletion layers in the channel formation regions of P channel MOS transistors Pa-Pd are widened. In N channel MOS transistors Na-Nd as well, when back gate voltage Vns is higher than ground voltage GND, depletion layers are wider than when ground voltage GND is applied to the back gates. Therefore, when P channel MOS transistors Pa-Pd and N channel MOS transistors Na-Nd are switched on and rendered conductive to form the channels, the widened depletion layers increase the channel sectional areas and the amount of moving carriers. Accordingly, MOS transistors Pa-Pd and Na-Nd are switched on and off at high speed, and the amount of drive current and the response speed are increased.
Even when the input signal applied to input node 101 makes a transition from the H level to the L level, MOS transistors Pa-Pd and Na-Nd are operated at high speed due to back gate voltages Vps and Vns, and the signal of output node 102 makes a transition from the H level to the L level.
Now, consider the case in which back gate voltage Vps from first voltage generation-circuit 110a is set to a voltage level higher than power supply voltage VDD in accordance with the control signal from control circuit 112a, and back gate voltage Vns from second voltage generation circuit 110b is set to a voltage level lower than ground voltage GND in accordance with the control signal from control circuit 112b.
In this case, the depletion layers of MOS transistors Pa-Pd and Na-Nd become narrower than when power supply voltage VDD and ground voltage GND are applied as the back gate voltages, and channel formation is suppressed. In this case, when the signal applied to input node 101 makes a transition from the L level to the H level, CMOS inverters IVa-IVd cause the output signal at output node 102 to make a transition from the L level to the H level. However, since the depletion layers are narrower and the channel sectional areas are accordingly smaller, the amount of moving carriers, the amount of current and the response speed are reduced.
Therefore, by adjusting the voltage levels of back gate voltages Vps and Vns output from voltage generation circuits 110a and 110b, the amount of drive current and the response speed of a semiconductor circuit can be adjusted depending on applications.
In order to reduce the response time to allow the high speed operation in the semiconductor integrated circuit device shown in FIG. 19, voltage Vps applied to the back gates of P channel MOS transistors Pa-Pd is set to the voltage level of Vps1 slightly lower than power supply voltage VDD, and voltage Vns applied to the back gates of N channel MOS transistors Na-Nd is set to the a voltage level of Vns1 slightly higher than ground voltage GND, as shown in FIG. 20. Thus, the back gate biases of MOS transistors Pa-Pd and Na-Nd are made slightly shallower and the depletion layers formed immediately under the channels are slightly widened. On the other hand, for the low speed operation, back gate voltage Vps is set to the voltage level of Vps2 slightly higher than power supply voltage VDD, and back gate voltage Vns of N channel MOS transistors Na-Nd is set to a voltage level slightly lower than ground voltage GND. Thus, the back gate biases of MOS transistors Pa-Pd and Na-Nd are made deeper, the depletion layers are made narrower, and the amount of drive current is reduced.
Back gate voltages Vps and Vns each determine the threshold voltage of an MOS transistor, and the threshold voltages of MOS transistors Pa-Pd and Na-Nd are changed according to the values of back gate voltages Vps and Vns. On the other hand, a current called a subthreshold leakage current is known in an MOS transistor.
FIG. 21 shows the relationship between a gate-to-source voltage Vgs and a drain current Ids in the subthreshold region of an N channel MOS transistor. In FIG. 21, the ordinate indicates drain current Ids in a logarithm scale and the abscissa indicates gate-to-source voltage Vgs. The threshold voltage of an MOS transistor is defined as a gate-to-source voltage causing a prescribed drain current to flow in an MOS transistor having a predetermined gate width. In FIG. 21, a curve I indicates gate-to-source voltage vgs and drain current Ids when the threshold voltage is Vth1, while a curve II indicates the relationship between drain current Ids and gate-to-source voltage Vgs of an MOS transistor having a threshold voltage Vth2. A region in which curves I and II change linearly is where drain current Ids decreases exponentially, and it is called a subthreshold region.
As shown in FIG. 21, a current of a certain magnitude flows in an MOS transistor even if gate-to-source voltage Vgs is 0V. Usually, this current is called a subthreshold leakage current. As the threshold voltage increases, the subthreshold leakage current decreases. However, the operation speed of an MOS transistor is lowered as the threshold voltage increases. If the back gate bias is made deeper (shifted in a negative direction) in an N channel MOS transistor, the threshold voltage is increased and the characteristic curve changes from curve I to curve II as shown in FIG. 21. The relationship between the drain current and the gate-to-source voltage of a P channel MOS transistor is obtained by inverting the sign of gate-to-source voltage Vgs of the graph shown in FIG. 21.
Therefore, as shown in FIGS. 20 and 21, when the back gate bias is made deeper and back gate voltages Vns2 and Vps2 are applied in the semiconductor integrated circuit device shown in FIG. 19, the threshold voltage becomes higher than when back gate biases Vns1 and Vps1 are applied, and the subthreshold leakage current decreases. In this case, however, back gate voltages Vns and Vps only have their voltage levels shifted from ground voltage GND and power supply voltage VDD, and the subthreshold leakage current cannot sufficiently be reduced. Especially, when a battery is used as a power supply as in the case of portable information terminal equipments, the value of the subthreshold leakage current in a standby cycle or a low speed operation cannot be ignored, and the battery life cannot be improved.
The prior art document (Japanese Patent Laying-Open No. 6-291267) which discloses the semiconductor integrated circuit device shown in FIG. 19 only describes adjustment of the response speed and the drive current amount according to its operational environment. In other words, it only considers the operation speed in the operation cycle of the semiconductor integrated circuit device and does not consider at all the problems associated with the subthreshold leakage current in the standby cycle or the low speed operation.
A structure for reducing the leakage current in-the standby cycle as described above is disclosed in, for example, Japanese Patent Laying-Open No. 6-21443. In this prior art, to the back gate of an N channel MOS transistor, a positive voltage Vp is applied in an active cycle (operation cycle) and ground voltage GND is applied in the standby cycle. FIG. 22 shows the relationship between the back gate voltage and the threshold voltage of the prior art N channel MOS transistor.
Now, consider the case in which the threshold voltage Vth of an N channel MOS transistor when a back gate-to-source voltage VBS (voltage measured relatively to the source voltage (ground voltage)) is a voltage Vb is 0.1V, and threshold voltage Vth when back gate-to-source voltage VBS is 0V is 0.4V as shown in FIG. 22. Since voltage Vb cannot exceed the built-in voltage (diffusion potential) Vpn (.about.1V) of a PN junction in this case, voltage Vb is smaller than voltage Vpn. Therefore, in order to satisfy a threshold voltage condition required for using voltage Vb, a characteristic curve having a considerably steep slope as shown in FIG. 22 should be realized. Since the slope of this characteristic curve is proportional to a substrate effect constant K, this substrate effect constant K should be larger. Substrate effect constant K is usually proportional to a product of the square root of substrate impurity concentration and the film thickness of a gate insulation film. Therefore, the impurity concentration of a substrate region (back gate region) needs to be higher to increase substrate effect constant K. In this case, the depletion layer is made narrower and the gate capacitance is accordingly increased, thus the high speed operation is not allowed (voltage Vb is a voltage which is applied for the high speed operation and its purpose cannot be achieved).
When the width of the depletion layer is narrower, since the electric field strength in the PN junction is inversely proportional to the width of the depletion layer, the electric field strength of the PN junction is increased, a junction break-down voltage is lowered, and the reliability of an element is deteriorated. When the impurity concentration of the substrate region is made higher, a diffusion current is caused in proportion to a difference between the impurity concentration of a substrate region and the impurity concentration of source/drain impurity regions of N channel MOS transistor. Accordingly, a reverse current (current which flows when a reverse bias voltage is applied to a PN junction), a leakage current and therefore current consumption are increased.
In the case of the characteristic curve shown in FIG. 22, threshold voltage Vth changes to a greater extent only with a slight change of back gate-to-source voltage VBS, thus making it difficult to accurately set a desired threshold voltage.